Semiconductor Research
With high-performance computing driving AI and other applications, heat accumulation in chips from processor operations and Joule heating threatens performance and reliability. We address chip- and package-level heat dissipation by improving the thermal properties of materials within the integrated circuit and thermal interface materials (TIM) bridging the chip to the heat sink.
To enhance package thermal performance (TIM enhancement), we form the thermal interface material (TIM) directly on the die backside via thin-film deposition, replacing conventional printing/coating, and complete die–substrate assembly through homo- or heterogeneous bonding. The process includes surface activation, nanometer-scale adhesion/diffusion-barrier layers, and low-temperature compression bonding to reduce interfacial thermal resistance and improve mechanical reliability. To address die-level hotspots, we adopt a hotspot-aware TIM architecture that pairs (i) power-map-guided local tailoring of TIM thickness/composition with (ii) an integrated lateral heat-spreading layer exhibiting high in-plane conductivity. This combination redistributes heat away from high-flux blocks, lowers peak junction temperature, and preserves a thin, uniform bondline elsewhere. This approach combines manufacturability with materials flexibility and provides a general solution for high-power, high-heat-flux packaging.
As Moore’s Law scaling slows, three-dimensional integrated circuits (3D ICs) have emerged as a compelling path to higher compute density and shorter interconnects. By vertically stacking logic, memory, and accelerators, 3D ICs reduce RC delay and energy per bit while boosting bandwidth. However, stacking also concentrates power and lengthens heat-evacuation paths, making die-level thermal management the primary limiter to performance and reliability. Hotspots originating from transistor switching and Joule heating in dense interconnects raise local junction temperatures; if that heat is not efficiently transported through the dielectric network and across multiple bonded interfaces to the external heat sink, the consequences are frequency throttling, timing errors, and premature failure. We target the chip-internal portion of the thermal pathway—where today’s low-k interlayer dielectrics and metal/dielectric interfaces dominate the thermal resistance and extend it across chip-to-chip interfaces, establishing a continuous, low-impedance route for heat to exit the stack. The anticipated outcome is a hotspot-resilient 3D integration platform that preserves the electrical advantages of low-k dielectrics while unlocking the latent thermal headroom required for next-generation HPC and AI systems.
Figure reference 1: https://ieeexplore.ieee.org/document/10413721
Figure reference 2: https://ieeexplore.ieee.org/document/11038409